Configurable RISC-V Core
A configurable RISC-V core that mines the custom instructions your code actually needs — and generates only the logic to run them. A clean, lean alternative to the heavyweight "custom cores" from Cadence Tensilica and MIPS ARC, without the baggage they carry.
From your code to owned silicon.
No needless overhead.
Incumbent configurable cores are bloated by design. Their generators bolt every optional feature onto a fixed, general-purpose template — so the RTL you ship is full of logic you never use. In a typical offering, adding even a single unused instruction — a NOP — can drag in on the order of 100,000 lines of supporting RTL.
We generate only what your design uses.
Our core is synthesized from the instructions your code mines — nothing more. The result is dramatically smaller, cleaner RTL: faster to verify, easier to close timing, cheaper in area and energy, and far simpler to own and maintain. Less silicon doing exactly your job.
One core, your priorities.
Minimum energy is only one dial. Tell us what matters most and we tune the mined extensions and microarchitecture to hit it.
Maximum Performance
Widen and specialize for the hottest kernels — the most throughput per clock for your workload.
Minimum Energy
Fuse operations and strip waste so each result costs the fewest joules — ideal for always-on and edge.
Minimum Area
Smallest footprint that still runs your code well — the most function per square millimeter.
The honest custom core.
Configurable processors aren't new — Cadence Tensilica and MIPS ARC built the category. What's new is the method and the discipline: we mine extensions automatically from your source with an LLVM-based pipeline, generate only the logic those extensions require, optimize to your chosen target, and deliver a core you fully own.
Specifications
| Base ISA | RISC-V, with mined custom extensions |
|---|---|
| Generated RTL | Only the logic your instructions use — no dead features |
| Optimization targets | Maximum performance · Minimum energy · Minimum area |
| Instruction discovery | LLVM-based analysis of your code's hot primitives |
| Deliverables | Custom core + GCC/Clang toolchain + instruction-set simulator |
| Category peers | Cadence Tensilica, MIPS ARC |
| Delivery | Synthesizable RTL — customer-owned |