Silicon IP, delivered pre-integrated.
High-performance and minimum-energy RISC-V cores, a programmable network-on-chip, fabric processors that scale up / out / across, inference and modem SoCs, automotive chiplets, and a deep peripheral IP library — connected through the NoC and handed to you as a working design, so your team skips integration.
RISC-V, from datacenter-class to minimum-energy.
High-Performance RISC-V Core
Superscalar RISC-V, 10-/16-wide, running Linux on FPGA today.
Learn more →Configurable RISC-V Core
Mines the custom instructions your code needs and generates only the logic to run them — a lean alternative to Tensilica and ARC. Tune for performance, energy, or area.
Learn more →Minimum-Energy Routing Core
A tiny RISC-V in every fabric router — programmable, field-patchable.
Learn more →Provably minimal energy, at the arithmetic.
One fabric, chip to datacenter.
Network-on-Chip with Programmable Routers
A routing core in every node; coherent + non-coherent; ships pre-connected to the cores.
Learn more →Fabric Processors
Inside-rack (1024×200G) and between-rack (96×400GbE) fabric processors.
Learn more →Scale-Across (DC-to-DC) Processor
Datacenter-to-datacenter: 100+ km reach, 51.2 Tbps, HBM-buffered.
Learn more →Ethernet MAC
Licensable IEEE 802.3 MAC — 10/100/1000, MII/GMII/RGMII/SGMII, config-driven unified core.
Learn more →Purpose-built engines.
Transformer/LLM Inference Accelerator
Systolic compute + fused attention; HBM3 @ 2 TB/s; MLIR stack.
Learn more →Digital Modem SoC (LTE/5G)
Full digital baseband PHY; LTE Cat-18 baseline, extensible to 5G NR.
Learn more →ADAS Sensor-Fusion Chiplet
2.5D chiplet; 30+ TOPS; ASIL-D capable; UCIe; ≤5 W.
Learn more →A 33-block peripheral IP library — ready to drop in.
Interrupt controllers, timers, serial I/O, automotive networking (CAN / CAN-FD / CAN-XL / LIN / SENT / Automotive Ethernet + TSN), data movement and storage, ISO-26262 safety, security, and debug — synthesizable RTL, independently verified, licensed as kits.
Browse the peripheral library